Digital signal processing (3.13.5)

Logic gates are electronic switching circuits. The output of a logic gate is dependent on the type of gate and the input. An input into a gate takes one of two forms:

• On – if a current is present. This is represented by 1.
• Off – if a current is not present. This is represented by 0.

There are three basic logic gates: AND gate, OR gate, and NOT gate.

• AND gates have an output of 1 if both inputs are 1.
• OR gates have an output of 1 if either input, or both inputs, are 1.
• NOT gates have an output that is opposite to their input.

Logic gates process digital information and are widely used in electronic systems, such as computer processors.

Logic gates can be combined together to achieve a particular outcome. This is known as combinational logic.

The output of a logic gate, or a combination of logic gates, can be determined using truth tables. Truth tables list all possible inputs along with their outcomes in ascending (binary) numerical order.

The total number of input combinations is given by 2ⁿ where n is the number of inputs.

There are three other logic gates that are formed by combining the basic logic gates:

• NAND – an AND gate followed by a NOT gate, producing the inverted output of an AND gate.
• NOR – an OR gate followed by a NOT gate, producing the inverted output of an OR gate.
• EOR/XOR – often called the exclusive OR gate

They are used so often that they have their own unique symbols.

• NAND gates have an output of 0 if both inputs are 1.
• NOR gates have an output of 0 if either input, or both inputs, are 1.
• EOR gates have an output of 1 if it has one input of 1 and one input of 0.

Truth tables for the NAND, NOR, and EOR gates can be constructed in the same way as the basic logic gates.

There are several identities, known as simplifications, in Boolean algebra that are necessary to understand logic circuits. By considering the truth table for the appropriate relationship and input variables, the simplification can be understood.

Two examples of this are shown in the image below.

Power consumption and cost increase with the number of logic gates and, therefore, circuit designers will aim to use the minimum number of gates to improve efficiency.

There are eight common simplifications:

A key skill is producing a logic circuit from a truth table that yields the desired outcome. This is done using the following steps:

• Write expressions in Boolean algebra for the information in the truth table by considering the conditions for the output to be true (equal to 1).
• Simplify the expression.

A simple example of drawing a logic circuit from a truth table is:

Consider when Z is true:

Write this as an expression in Boolean algebra, remembering that ‘+’ means or:

Simplify this expression by collecting common terms and using simplifications:

Interpret:
Z is true when either not A and B are true, or when A is true, so:

This circuit can be simplified to just an OR gate.

Many logic circuits involve changing input signals. These are often time dependent and follow a predefined sequence. They are called sequential logic circuits and are used for timing and counting.

Sequential logic circuits use circuit block diagrams, such as the one below, for a binary counter.

Inputs:

• CK is the clock input. This is the signal that the circuit counts.
• U/D is the up/down input. When it is equal to 1, the circuit counts up, and when it is equal to 0, the circuit counts down.
• MR is the master reset input. When it equals 1, all outputs will reset to 0.

Outputs:

• Q₀ to Q_N are the counter outputs.
• Q₀ is known as the least significant bit (LSB). Each input produces a difference of 1, and it changes the most frequently due to its proximity to the clock input.
• Q_N is the most significant bit (MSB) and is furthest from the clock input. It changes the least frequently and depends on the number of bits in the counter.

A timing diagram illustrates how the output of each bit varies with each clock pulse.

A clock change from 0 to 1 is called a rising edge.

The diagram shows that this counter is rising-edge triggered, as its outputs change only when the clock input changes from 0 to 1.

The maximum value an N-bit binary counter can reach is , after which it will reset. The diagram shows a 4-bit counter; it will count 15 pulses before resetting to 0000.

The pulse rate of a counter is defined as the frequency of the output pulses, and each bit has a different frequency. The frequency of Q₀ is half that of the clock, whilet the frequency of Q₁ is half that of Q₀ and so on. This characteristic allows it to be used as a frequency divider.

A simple binary counter can be adapted to count up to a predefined value before resetting by adding a logic gate. This adaptation allows the final value to be any number, unlike a binary counter, which can only have a final value that is a power of 2.

These circuits are called modulo- n counters and will count up to before resetting on n. For example, a modulo-13 counter will count up to 12 and then reset.

The modulo-13 counter circuit shows that the AND gate will give an output of 1 when both inputs are 1. In binary representation, 12 is written as 1100 and occurs when Q₀ = 0, Q₁ = 0, Q₂ = 1, and Q₃ = 1.The AND gate therefore, must be connected to Q₂ and Q₃. When the counter reaches 1100 the AND gate output provides an input of 1 to the master reset input, and the circuit resets.

Any reset value can be created using a combination of AND gates.

A binary coded decimal (BCD) counter is used in digital displays to provide a 0–9 output. It uses a modulo-10 counter created by a 4-bit binary counter with an AND gate connected to Q₀ and Q₃, which will count to 1001 (=9) before resetting.

Several digital displays can be connected in series to display numbers with multiple digits. These blocks have an extra output signal called the carry-out (C₀). This output signal is connected to the clock input of another counter. Each time the counter to the left reaches 10, the counter on the right receives an input of 1, advancing its count by 1.

A sequencer is a device that performs operations that must be done in a particular order.

This can be done using a Johnson or decade counter. A Johnson counter has 10 counter outputs; however, it is not the same as a 9-bit binary counter. Rather than being rising-edge triggered, the outputs are sequentially triggered.

For example, Q₁ switches to 1 on the rising edge of the first clock pulse, and on the rising edge of the second clock pulse, Q₂ switches to 1. This sequence continues until Q₉ becomes 1.

It is important to note the difference in the value of Q₀ when the count resets between a binary counter and a Johnson counter. As the timing diagram shows, in a Johnson counter, Q₀ starts with a value of 1. Exactly one output is high at any time. At count 0, Q₀ is high; at count 1, Q₁ is high; and so on.

An example of a real-life application of a Johnson counter is shown below.

The circuit runs the following sequence of operations and repeats every 10 seconds:

• The heater is on for 3 seconds.
• The heater is off for 3 seconds.
• The heater is rotated for 2 seconds.

A pulse generator is a circuit that will produce continuous clock pulses. These oscillating circuits are known as astables.

They switch from on to off with a constant time period and do not have a stable state.

The period (t_p) is the time for one complete cycle. This is generally measured from the start of one pulse to the start of the next.

Astables comprise a resistor–capacitor (RC) combination along with a NOT gate. The NOT gate is a specialised gate with two switching thresholds and exhibits hysteresis. In a circuit diagram, the NOT gate symbol contains the hysteresis symbol to identify it as a specialised NOT gate.

• Initial input into the NOT gate is 0 as the capacitor is uncharged.
• Initial output from the NOT gate is 1.
• The capacitor begins to charge through the resistor.
• The potential difference across the capacitor reaches the upper switching threshold.
• The input to the NOT gate becomes 1.
• The output from the NOT gate switches to 0.
• The capacitor begins to discharge through the resistor.
• The potential difference across the capacitor reaches the lower switching threshold.
• The input to the NOT gate switches to 0, and the cycle begins again.

A normal NOT gate has a single switching threshold at approximately half of the supply potential difference (V_s).

For a NOT gate with hysteresis, the lower switching threshold is typically one-third of the supply potential difference, and the upper threshold is around two-thirds of the supply potential difference.

For astables, t_on is the time it takes for the potential difference to increase from and it is approximately 0.7 times the time constant of the circuit.

The charging and discharging circuits are the same, so and will be equal, meaning the period will be twice the time constant.

The clock rate is therefore dependent on the resistance and capacitance values of the circuit: